1. Field of the Invention
The present invention relates to electronic circuits, and more specifically to a phase locked loop circuit having a phase comparator, a charge pump, a loop filter, and a voltage controlled oscillator.
2. Description of Related Art
In electronic circuits, it is often required to generate a highly precise reference frequency whose value is programmable for various purposes. For example, read and write channels for hard disk drives (i.e., the magnetic disks operating as mass storage for a processor) require a circuit to generate a programmable reference frequency to maintain at constant density the data stored on the magnetic disk. This function is commonly obtained through the use of phase locked loop (PLL) circuits that generate a wide range of frequencies, which can be set through the selection of the division value of two dividers, from a high precision fixed clock signal.
FIG. 1 shows a block diagram of a conventional phase locked loop 1. The phase locked loop 1 includes a phase comparator 2, a charge pump circuit 3, a filter loop 4, and a voltage controlled oscillator 5 that are connected in series on a main branch of the phase locked loop 1. A feedback branch departs from the voltage controlled oscillator 5 receiving an output frequency signal FOUT at a frequency divider block 6, which divides by an integer number M. The divided frequency signal FD is sent to the input of the phase comparator 2, which also receives a reference frequency signal FR.
The phase comparator 2 detects the phase difference between the divided frequency signal FD and the reference frequency signal FR and issues two signals UP and DOWN, which are representative of the phase error or displacement and whose trend is shown in FIG. 2. Signals UP and DOWN consist of pulses whose length difference is proportional to the phase displacement between the divided frequency signal FD and the reference frequency signal FR. As shown in FIG. 2, the signal UP is used to pull the signal DOWN to the low logic state (i.e., to drive its falling edge). The signal DOWN is pulled to the high logic state where it remains for a time proportional to the phase displacement, then the signal UP is generated, which remains at the high logic level only for the time required by the logic gates to drive the falling edge of both signals UP and DOWN.
The phase comparator 2, which is also known as a sequential phase comparator, is particularly suited for those applications where input signals also initially differ in their frequencies. Under steady conditions or when the divided frequency signal FD and the reference frequency signal FR are in phase, pulses are at their minimum length and have an equal length. Both signals UP and DOWN drive the charge pump circuit 3 that converts them into current pulses IU and ID. Current pulses IU and ID are then transformed into control voltage displacements V1 and V2 for the voltage controlled oscillator through the loop filter 4, which is a balanced filter RC that will be described below with reference to FIG. 4.
The control voltages displacements V1 and V2 produce a change in the oscillating frequency of the voltage controlled oscillator 5 (i.e., the frequency of the output signal FOUT) that is proportional to the phase difference between the divided frequency signal FD and the reference frequency signal FR detected by the phase comparator 2. Thus, the phase locked loop 1 in steady state will reach a condition where the rising edges or falling edges of the divided frequency signal FD and reference frequency signal FR are phase aligned (i.e., the phase error between them is zero).
FIG. 3 shows a conventional charge pump circuit having current generators connected between the filter terminals and supply lines and ground. As shown, the charge pump circuit 3 includes two fixed current generators I1 and I2 located between a supply voltage VDD and one of two nodes N1 and N2, respectively. The nodes N1 and N2 represent the terminals of the loop filter 4. Two further switching current generators I3 and I4 are connected between ground GND and nodes N1 and N2 through two switches S3 and S4, respectively. Fixed current generators I1 and I2 are always operating so as to determine a constant current injection on nodes N1 and N2. Switches S3 and S4, which are respectively driven by the signals UP and DOWN that are representative of the phase error, determine the connection between nodes N1 and N2 and the switching current generators I3 and I4 as follows.
In a first configuration, switching current generators I3 and I4 are connected with node N2, whereas node N1 only receives the current supplied by fixed current generator I1. In a second configuration, switching current generators I3 and I4 are connected with node N1, whereas node N2 only receives the current supplied by fixed current generator I2. The loop filter 4 carries out an integrating operation so that voltage displacement is established on nodes N1 and N2, which correspond to control voltages V1 and V2 of the voltage controlled oscillator 5.
Moreover, a feedback path is provided to lead back control voltages V1 and V2 and drive the current output of fixed current generators I1 and I2. Thus, the conmnon mode voltage related to nodes N1 and N2 is maintained constant. The charge pump circuit 3 substantially provides two symmetric branches, each one of which has a constant current generator and a pulsed current generator that inject their currents in the nodes common to the filter and to the differential inputs of the voltage controlled oscillator. For this reason, the charge pump circuit 3 can also be considered as having two differential branches.
FIG. 4 shows the loop filter 4. This is a balanced filter RC having a series connected resistor R and first capacitor C1 connected in parallel with a second capacitor C2. An equivalent resistor REQ is shown in parallel with loop filter 4 to represent the series resistance of fixed current generators I1 and I2. The loop filter 4 is especially relevant because it determines the dynamics of the phase locked loop 1, and consequently its performance.
The conventional charge pump circuit described above has drawbacks. First, because two current generators are always connected in parallel with the filter and these current generators do not have an infinite resistance, a current flow will result between the input filter nodes with an ensuing undesired voltage displacement between the two points controlling the voltage controlled oscillator. As a result, the output signal from the phase locked loop is affected by a phase offset that cannot be removed from the reaction loop and consequently there is a frequency output differing from that which is desired.
A further drawback of the charge pump circuit of FIG. 3 arises because the switching current generators and switches are provided as a sole circuit having a differential pair of P-channel MOS transistors that operate both as switches and current generators. The use of P-channel MOS transistors causes problems due to their slow speed and the difficulty of providing two symmetric P-channel transistors.
In view of these drawbacks, it is an object of the present invention to overcome the above-mentioned drawbacks and to provide an improved phase locked loop.
Another object of the present invention is to provide a phase locked loop with a charge pump circuit that does not cause input voltage displacements at the voltage controlled oscillator so as to provide a substantially zero phase offset.
A further object of the present invention is to provide a phase locked loop having a charge pump circuit with a substantially infinite impedance with respect to the filter.
Yet another object of the present invention is to provide a phase locked loop having switching current generators with a high parameter symmetry and that are not substantially affected by any changes in technological process parameters.
One embodiment of the present invention provides a phase locked loop that includes a phase comparator, a charge pump circuit, a loop filter, and a voltage controlled oscillator. The charge pump circuit includes two symmetric branches, feedback paths, and circuit breaking switches. Each of the symmetric branches has a constant current generator and a pulsed current generator, with one terminal of the loop filter being connected to one of the symmetric branches and the other terminal of the loop filter being connected to the other of the symmetric branches. The feedback paths control the constant current generators based on voltages at the terminals of the loop filter, and each of the circuit breaking switches couple one of the pulsed current generators and the corresponding terminal of the loop filter. The pulsed current generators supply a first current whose amplitude is proportional to an amplitude of a second current supplied by the constant current generators through the duty cycle of the first current. In a preferred embodiment, the circuit breaking switches are controlled by phase error signals from the phase comparator.
Another embodiment of the present invention provides a method for controlling a charge pump circuit in a phase locked loop having a phase comparator that supplies phase error signals to the charge pump circuit. The charge pump circuit converting the phase error signals into current signals integrated by a loop filter to drive a voltage controlled oscillator, and has two symmetric branches each including a constant current generator and a pulsed current generator. According to the method, the constant current generators are controlled through feedback paths that maintain a constant common mode voltage on the two terminals of the loop filter, and each pulsed current generator is connected with the corresponding terminal of the loop filter after a transition of a corresponding one of the phase error signals. The constant current generators are sized to supply a first current with a first current amplitude substantially proportional to a second amplitude of a second current that is supplied by the pulsed current generators through the ratio of a period of the phase error signals to a time interval during which each of the phase error signals is active.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only and various modifications may naturally be performed without deviating from the present invention.